`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/09/09 09:24:51
// Design Name: 
// Module Name: uart_top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////
`include "sys_parameter.vh"

module uart_top #
(
    parameter UART_CLK_PARAM  = 32'd100_000_000,
    parameter UART_BPS_TX     = 32'd115_200    


)(
    input               sys_clk  ,
    input               sys_rst_n,

    output wire         uart_txd 

    // input  [1*8-1 :0]   status_RF_workMode,
    // input  [4*8-1 :0]   status_RF_workFre ,
    // input  [16*8-1:0]   status_RF_Att     
);
    //#### Uart2SigBoard_tx ####
    uart2device_tx #(
        .UART_CLK_PARAM    ( UART_CLK_PARAM  ),    
        .UART_BPS_TX       ( UART_BPS_TX     ))    
    uart2device_tx (
        .clk               ( sys_clk            ),
        .sys_rst_n         ( sys_rst_n          ),
        
        .status_RF_workMode( 8'd1   ),
        .status_RF_workFre ( 32'd1  ),
        .status_RF_Att     ( 12'd1      ),

        .uart_txd          ( uart_txd           )
    );


endmodule  //Uart2SigBoard_top